-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
--2009-6-4
-------------------------------------------------------------------------------
-- vhdl training hfdy
-- hardware = lt-cpld
-------------------------------------------------------------------------------
--entity
-------------------------------------------------------------------------------
entity test is
port(
clk: in std_logic;
clk2: out std_logic;
keys: in std_logic_vector(7 downto 0);
dac: out std_logic_vector(7 downto 0)
);
end test;
-------------------------------------------------------------------------------
architecture rtl of test is
signal acc: std_logic_vector(31 downto 0);
signal sum: std_logic_vector(31 downto 0);
signal add: std_logic_vector(7 downto 0);
signal data: std_logic_vector(7 downto 0);
signal bcc: std_logic_vector(7 downto 0);
begin
-------------------------------------------------------------------------------
clk2<=Ƈ'
bcc<=acc(31 downto 24);
-------------------------------------------------------------------------------
process(clk,acc,sum,keys)
begin
if clk'event and clk=Ɔ' then
acc<=sum;
end if;
sum<=acc+keys+"00000000000000001000000000000000";
end process;
-------------------------------------------------------------------------------
process(bcc,add,data)--sin_rom
begin
if clk'event and clk=Ƈ' then
if bcc<"01000000" then
add<=bcc;
dac<=data;
elsif bcc<"10000000" then
add<="01111111"-bcc;
dac<=data;
elsif bcc<"11000000" then
add<=bcc-"10000000";
dac<="11111111"-data;
elsif bcc<="11111111" then
add<="11111111"-bcc;
dac<="11111111"-data;
end if;
case add is
when"00000000"=>data<="10000000";
when"00000001"=>data<="10000011";
when"00000010"=>data<="10000110";
when"00000011"=>data<="10001001";
when"00000100"=>data<="10001100";
when"00000101"=>data<="10001111";
when"00000110"=>data<="10010010";
when"00000111"=>data<="10010101";
when"00001000"=>data<="10011000";
when"00001001"=>data<="10011011";
when"00001010"=>data<="10011110";
when"00001011"=>data<="10100001";
when"00001100"=>data<="10100100";
when"00001101"=>data<="10100111";
when"00001110"=>data<="10101010";
when"00001111"=>data<="10101101";
when"00010000"=>data<="10110000";
when"00010001"=>data<="10110011";
when"00010010"=>data<="10110110";
when"00010011"=>data<="10111001";
when"00010100"=>data<="10111011";
when"00010101"=>data<="10111110";
when"00010110"=>data<="11000001";
when"00010111"=>data<="11000011";
when"00011000"=>data<="11000110";
when"00011001"=>data<="11001001";
when"00011010"=>data<="11001011";
when"00011011"=>data<="11001110";
when"00011100"=>data<="11010000";
when"00011101"=>data<="11010010";
when"00011110"=>data<="11010101";
when"00011111"=>data<="11010111";
when"00100000"=>data<="11011001";
when"00100001"=>data<="11011011";
when"00100010"=>data<="11011110";
when"00100011"=>data<="11100000";
when"00100100"=>data<="11100010";
when"00100101"=>data<="11100100";
when"00100110"=>data<="11100101";
when"00100111"=>data<="11100111";
when"00101000"=>data<="11101001";
when"00101001"=>data<="11101011";
when"00101010"=>data<="11101100";
when"00101011"=>data<="11101110";
when"00101100"=>data<="11101111";
when"00101101"=>data<="11110001";
when"00101110"=>data<="11110010";
when"00101111"=>data<="11110100";
when"00110000"=>data<="11110101";
when"00110001"=>data<="11110110";
when"00110010"=>data<="11110111";
when"00110011"=>data<="11111000";
when"00110100"=>data<="11111001";
when"00110101"=>data<="11111010";
when"00110110"=>data<="11111011";
when"00110111"=>data<="11111011";
when"00111000"=>data<="11111100";
when"00111001"=>data<="11111101";
when"00111010"=>data<="11111101";
when"00111011"=>data<="11111110";
when"00111100"=>data<="11111110";
when"00111101"=>data<="11111110";
when"00111110"=>data<="11111110";
when"00111111"=>data<="11111111";
when others=> null;
end case;
end if;
end process;
-------------------------------------------------------------------------------
end rtl;
