倍频器。这是e文说明： this frequency doubler using a single 4069 hex inverter ic, a frequency doubler can be constructed to give an output pulse train whose frequency is twice that of a squarewave input signal. the signal is applied to the input of n1. it should be a squarewave with a duty-cycle of approximately 50% at level compatible with cmos logic (3-15v peak to peak depending on supply voltage). the input signal is buffered and inverted by n1, and inverted again by n2, so the outputs a and b of n1 and n2 are squarewave signals 180° out of phase. the output of n1, is differentiated by c1 and r1 and the output of n2 is differentiated by c2 and r2, giving two spike waveforms of c and d, 180° out of phase. the signals are buffered, inverted and shaped by n3 and n4. these are then combined in a nor gate consisting of d1, d2, r3 and n5, and finally inverted by n6 to give the frequency twice that of the input signal. the circuit will operate over a wide frequency range. with the component values shown the width of pulses in e and f point is about 500ns, so the duty cycle of the output will be 50% when the frequency is 1mhz, when the input frequency is 500khz.by a.m. bosschaert
