有谁会用cpld [复制链接]

最近想做个高频的东东，但是单片机做不了那么高的频率
故改用cpld来做，初学这东西。比较难理解。

以下是我写的分频器的程序，错误有18处。还请高人指点。

library ieee;
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all

entity div is
port(clk:in std_logic;
    q :out std_logic
    );
end div;

architecture div5 of div is
begin
constant duty :integer=5;
constant pr2 :integer=10;
signal   cunt :integer range 0 to 10;
process(clk)
begin
if clk=Ƈ' then
  elsif (cunt<=duyt) then
  cunt<=cunt+1;
  q=Ɔ'
  elsif (cunt>=duty) then
  cunt<=cunt+1;
  q=Ƈ'
else
    cunt<=Ɔ'
    q=Ɔ'
end if;
end if;
end if;
end process;
end div;

以下自己排错后 还有四个错误

library ieee;
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all

entity div is
constant duty :integer=5;
constant pr2 :integer=10;
port(clk:in std_logic;
    q out std_logic
  );
end div;

architecture div10 of div is
signal cunt :integer range 0 to 10;
begin
process(clk)
  if clk=Ƈ' then
  elsif (cunt<=duyt) then
  cunt<=cunt+1;
  q=Ɔ'
  elsif (cunt>=duty) then
    cunt<=cunt+1;
    q=Ƈ'
  else
  cunt<=Ɔ'
  q=Ɔ'
end if;

end process;
end div;

搞了好久终于搞定了

差点让我崩溃，废话不说了。直接上图和程序。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity div is
generic( duty:integer:=5 ;
      time:integer:=10  
      );  
port(clk:in std_logic;
    q :out std_logic
    );
end div;

architecture div10 of div is    
signal cunt :integer range 0 to time-1 ;
begin
process(clk)
begin  
  if rising_edge(clk) then
    q<=Ƈ'
    if cunt<duty then
    q<=Ɔ'
    cunt<=cunt+1;

  elsif cunt<time-1 then
    cunt<=cunt+1;
  else
  cunt<= 0 ;
end if;
end if;
end process;
end div10;

diy精神，恭喜。