已经找到了原来的资料，谁能解释一下
pll03a and pll08a
pll frequency synthesizer
overview
this 27 mhz band, pll frequency synthesizer lsi chip is designed specifically for cb transceivers.
it incorporates pll circuitry and a controller for cb applications on a single cmos chip.
the pll-circuit use a 7 bit rom programmable divide-by-n counter. the rom-table is programmed from factory to 40 channels.
pin name description
1 vcc positive supply voltage
2 ri referency oscillator input
3 ld1 loop detected 1
4 ld2 loop detected 2
5 ld3 loop detected 3
6 pd phase detector output
7 t/r transmit=high receive=low
8 f in vco frequency input
9 p6 programmable input 6
10 p5 programmable input 5
11 p4 programmable input 4
12 p3 programmable input 3
13 p2 programmable input 2
14 p1 programmable input 1
15 p0 programmable input 0
16 gnd ground
programming chart for
pll03a (u.s. - am)
pll08a (eec - fm)
channel rx
divided by tx
divided by
1 1206 1297
2 1208 1299
.. .... ....
22 1258 1349
.. .... ....
40 1294 1385
notes:
special divided-by-2 circuit in tx mode change referency divider output to 2.5khz steps.
91-count upshifts on tx provides 455khz offset for receiver if mixing when vco frequency is doubled.
since chip cannot divide vco directly, it is down-mixed with the 10.240 mhz referency oscillator signal, producing
6 mhz outputs (rx mode) and 3 mhz outputs (tx mode) into dividers. standard 16 mhz vco is used.
pll08a contains only the first 22 fcc channels for eec use, otherwise both chips are identical.
example of vco determination, channel 1:
1206 x 5 khz + 10.240 mhz = 16.270 mhz (rx-mode)
1297 x 2.5 khz + 10.240 mhz = 13.4825 mhz (tx-mode)
(13.4825 mhz x 2 = 26.965 mhz)
