最近做东西,处于验证设计阶段。故要求操作越简单越好
本来是留了个计算机接口(我连api多写好了),简单的就用一个按键就可以操作
但是按键往往有抖动,所以写了个带单稳的按键消振程序
下面是用verilog写的,第一次用verilog写东西。觉得语法和c差不多
但是写程序的思路却变换的太多,c是串行的而verilog是并行的。
以下程序仅供学习verilog, fpga的菜鸟们借鉴之用。
module digital(clk,puls,en,s1,s2,led1,led2,clock);
input clk,en,s1,s2;
output puls,led1,led2,clock;
reg [8:0] cunt_s,cunt_on,cunt_off,temp_on=9'b100000000,temp_off=0;
reg [2:0 ] cunt_m;
reg [24:0] clock_s;
reg [24:0] cunt_l;
reg led1,led2,clock,flg_k;
wire s1,s2,en,clk;
reg puls,flg;
always @(posedge clk)//--------------puls occur
begin
if(flg==1'b1) begin
if(cunt_on==9'b100101100) begin
cunt_on<=temp_on;
puls<=1'b1;
flg<=1'b0;
end
else
begin
cunt_on<=cunt_on+1'b1;
end
end
if(!flg) begin
if(cunt_off==9'b100101100) begin
cunt_off<=temp_off;
puls<=1'b0;
flg<=1'b1;
led1<=~led1;
end
else
begin
cunt_off<=cunt_off+1'b1;
end
end
end
always@(posedge led2)
begin
if(temp_on<=9'b000111111) begin
temp_on<=9'b100000000;
end
else begin
temp_on<=temp_on-9'b000001111;
end
end
always@(posedge clk)//单稳消振
begin
if(s2==1'b0) begin
flg_k=1'b1;
end
if(flg_k==1'b1) begin
cunt_l<=cunt_l+1'b1;
if(cunt_l==24'b111111111111111111111111) begin
cunt_l<=24'b000000000000000000000000;
led2<=1'b1;
flg_k<=1'b0;
end
else begin
cunt_l<=cunt_l+1'b1;
led2<=1'b0;
end
end
end
endmodule